| PART |
Description |
Maker |
| XC3190A |
Logic Cell Array Families
|
XILINX
|
| XC2018-70PC84CI |
Logic Cell Array
|
Xilinx, Inc.
|
| HER303 HER302 |
TECHNICAL SPECIFICATIONS OF HIGH EFFICIENCY RECTIFIER
28000 GATE 3.3 VOLT LOGIC CELL ARRAY - NOT RECOMMENDED for NEW DESIGN
|
DC Components Co., Ltd.
|
| HER201G HER208G HER202G HER203G HER204G HER205G HE |
5000 GATE 3.3 VOLT LOGIC CELL ARRAY - NOT RECOMMENDED for NEW DESIGN 2.0安培。玻璃钝化高效整流二极管
2.0 AMPS. GLASS PASSIVATED HIGH EFFICIENCY RECTIFIERS
|
Jinan Gude Electronic Device Co., Ltd.
JGD[Jinan Gude Electronic Device]
|
| AN1318 |
INTERFACING BETWEEN LVDS AND HIGH SPEED DIFFERENTIAL LOGIC FAMILIES
|
STMicroelectronics
SGS Thomson Microelectronics
|
| MAX3.00A EPM3032ALC44-10 EPM3032ALC44-4 EPM3032ALC |
Programmable logic , 128 macrocells, 8 logic array blocks, 96 I/O pins, 7ns
Programmable logic , 128 macrocells, 8 logic array blocks, 96 I/O pins, 5ns
Programmable logic , 128 macrocells, 8 logic array blocks, 96 I/O pins, 10ns
Programmable logic , 64 macrocells, 4 logic array blocks, 66 I/O pins, 7ns
Programmable logic , 64 macrocells, 4 logic array blocks, 66 I/O pins, 4ns
Programmable logic , 64 macrocells, 4 logic array blocks, 66 I/O pins, 10ns
Programmable logic , 32 macrocells, 2 logic array blocks, 34 I/O pins, 7ns
Programmable logic , 32 macrocells, 2 logic array blocks, 34 I/O pins, 4ns
Programmable logic , 32 macrocells, 2 logic array blocks, 34 I/O pins, 10ns
Programmable Logic Device Family
|
Altera Corporation
|
| XC2S100-5FG256C XC2S100-5FG256I XC2S100 XC2S15-5VQ |
Spartan-II FPGA Family Data Sheet
30000 SYSTEM GATE 2.5 VOLT LOGIC CELL AR - NOT RECOMMENDED for NEW DESIGN FPGA, 216 CLBS, 30000 GATES, 263 MHz, PQFP144
100000 SYSTEM GATE 2.5 VOLT LOGIC CELL A - NOT RECOMMENDED for NEW DESIGN FPGA, 600 CLBS, 100000 GATES, 263 MHz, PBGA256
150000 SYSTEM GATE 2.5 VOLT LOGIC CELL A - NOT RECOMMENDED for NEW DESIGN FPGA, 864 CLBS, 150000 GATES, 263 MHz, PBGA456
200000 SYSTEM GATE 2.5 VOLT LOGIC CELL A - NOT RECOMMENDED for NEW DESIGN FPGA, 1176 CLBS, 200000 GATES, 263 MHz, PBGA256
200000 SYSTEM GATE 2.5 VOLT LOGIC CELL A - NOT RECOMMENDED for NEW DESIGN FPGA, 1176 CLBS, 200000 GATES, 263 MHz, PBGA456
100000 SYSTEM GATE 2.5 VOLT LOGIC CELL A - NOT RECOMMENDED for NEW DESIGN FPGA, 600 CLBS, 100000 GATES, 263 MHz, PQFP144
30000 SYSTEM GATE 2.5 VOLT LOGIC CELL AR - NOT RECOMMENDED for NEW DESIGN FPGA, 216 CLBS, 30000 GATES, 263 MHz, PQFP100
150 000 SYSTEM GATE 2.5 VOLT FPGA (IQ AU - NOT RECOMMENDED for NEW DESIGN
15000 SYSTEM GATE 2.5 VOLT LOGIC CELL AR - NOT RECOMMENDED for NEW DESIGN
50000 SYSTEM GATE 2.5 VOLT LOGIC CELL AR - NOT RECOMMENDED for NEW DESIGN
Spartan-II FPGA Family
Second generation ASIC replacement technology
|
Xilinx, Inc.
XILINX INC
|
| EPM3128ATC EPM3256ATC EPM3032ATC EPM3064A EPM3128A |
Programmable Logic , 64 Macrocells, 4 Logic Array Blocks, 66 I/o Pins, 10ns
Programmable Logic Device Family
Programmable Logic , 128 Macrocells, 8 Logic Array Blocks, 96 I/o Pins, 10ns
|
ALTERA[Altera Corporation]
|
| PA7536SI-15 PA7536 PA7536J-15 PA7536JI-15 PA7536P- |
PEEL Array-TM Programmable Electrically Erasable Logic Array
|
ANACHIP[Anachip Corp]
|
| PAL20L4-7DC PAL20L4-7JC PAL20L4-7PC PAL20L6-7DC PA |
24-pin TTL Programmable Array Logic 24针的TTL可编程阵列逻辑
24-pin TTL Programmable Array Logic OT PLD, 25 ns, PDIP24
24-pin TTL Programmable Array Logic OT PLD, 20 ns, PDIP24
24-pin TTL Programmable Array Logic OT PLD, 35 ns, PDIP24
24-pin TTL Programmable Array Logic OT PLD, 25 ns, CDIP24
24-pin TTL Programmable Array Logic OT PLD, 20 ns, CDIP24
24-pin TTL Programmable Array Logic OT PLD, 20 ns, PQCC28
24-pin TTL Programmable Array Logic OT PLD, 10 ns, CDIP24
24-pin TTL Programmable Array Logic OT PLD, 18 ns, PDIP24
24-pin TTL Programmable Array Logic OT PLD, 15 ns, CDIP24
24-pin TTL Programmable Array Logic OT PLD, 35 ns, PQCC28
|
Advanced Micro Devices, Inc.
|
| CS91 |
Standard cell array
|
FUJITSU[Fujitsu Media Devices Limited]
|
| XC3342 XC3330 XC3390 |
HardWire Logic Cell Arrays
|
Xilinx, Inc.
|
|
